This invention relates to processes for the fabrication of integrated circuit devices comprising double polycrystalline silicon layers, more particularly to processes for obtaining circuit structures with two self-aligned polycrystalline silicon layers in MOS (Metal Oxide Semiconductor)-type integrated circuits. As a rule, such double polycrystalline silicon layers are produced by first forming a continuous oxide layer on a polycrystalline silicon substrate, and then forming on the oxide layer, one after another, a first polycrystalline silicon layer, an intermediate oxide layer, and a second polycrystalline silicon layer. "Two-level" polycrystalline silicon circuit structures can then be obtained therein to form memory storage cells, capacitors, interconnecting lines and other circuit elements. Some of these structures then call for a high degree of alignment between the two polycrystalline silicon layers; this is, for instance, indispensable for the polycrystalline silicon gates of memory storage cells.
A common process used to produce structures with two aligned polycrystalline silicon layers, and which we may consider as the nearest prior art method to that of the present invention, is described in U.S. Pat. No. 4,142,926 to Morgan.
According to the Morgan process, the double polycrystalline silicon layer is formed in the usual manner, but only one of the two polycrystalline layers is doped appropriately.
Using conventional masking and etching techniques, a structure having the desired circuit configuration is defined in the second polycrystalline silicon layer; this structure forms the upper level of the desired two-level circuit structure.
This upper polycrystalline silicon structure is used as a mask in a subsequent etching operation for the elimination of the remaining exposed parts of the intermediate oxide layer.
Thereafter, the exposed parts of the first polycrystalline silicon layer are also etched until they are completely eliminated by an etching operation that acts selectively on the first layer only, precisely because of the fact that one of the two polycrystalline silicon layers is doped, while the other is not.
In this operation, the same structure formed in the second polycrystalline silicon layer, which is left unaltered or nearly so by the etching, acts as a mask; thus, a circuit structure is obtained in the first underlying polycrystalline silicon layer which is automatically self-aligned with that of the second layer with which it forms the desired two-level circuit structure.
This process is used mainly for the fabrication of programmable read-only memories (PROMs), comprising MOS-type floating-gate field-effect memory devices.
The upper gate of the device is obtained from the second polycrystalline silicon layer by masking the gate and by subsequent etching of the polycrystalline silicon not protected by the mask. This is followed by the elimination of the exposed parts of the intermediate oxide layer which, in turn, is followed, as stated above, by the etching of the first polycrystalline silicon layer by means of a reagent that acts selectively only on the first polycrystalline silicon layer in the parts where the latter is exposed.
The lower gate of the storage device is formed in this manner, so that it is automatically aligned with the upper gate.
Thereupon, using prior art implanting, depositing and diffusing techniques, a source region and a drain region, which are located adjacent to the gate region, are formed in the substrate through windows that have been opened in the lower oxide layer.
The process described above enables the self-alignment of the two-level polycrystalline silicon circuit structures, but it also has disadvantages that cannot be overlooked whenever one desires to reduce the integrated circuit device areas to a minimum.
As is well known, selective etchings of the type in use today are of the isotropic type so that, by acting on the polycrystalline silicon of the first layer with equal energy in all directions, it not only eliminates therefrom the parts not protected by the overlying oxide and polycrystalline mask of the second layer, but it also etches the edge of the protected parts, forming an undercut beneath the oxide. Therefore, the area of the "self-aligned" structure made out of the first polycrystalline silicon layer is, in reality, smaller than that of the structure of the second layer.
The difference between the areas, expressed as a percentage, is more significant as the area of the overall structure is decreased, and it constitutes an unnecessary loss of the available area used for the integrated circuit device.
For example, in the case of storage cells in which the capacitive effect between the two polycrystalline silicon layers is utilized for storing and transferring the data as voltages, a harmful reduction of the effective area of the capacitor formed by the gates results. Therefore, whenever integration techniques are adopted that involve the same type of doping of both of the polycrystalline silicon layers, the above noted process can no longer be used, since it is based on a selective etching which is dependent upon the doping of only one of the two layers.
At this point it should be noted that it is not possible to plasma etch the polycrystalline silicon of the first layer, since there is a danger that the exposed monocrystalline silicon would be etched excessively and the other parts of the device contaminated.